Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon CMOS with MTJ technology, is a major emerging technology that is highly competitive with existing semiconductor memories such as SRAM, DRAM, Flash, etc.
A MRAM bit is generally comprised of at least one magnetic tunneling junction (MTJ) cell that consists of a thin tunnel barrier layer made of a non-magnetic dielectric material such as AlOx or MgO that is sandwiched between a set of ferromagnetic layers. One of the ferromagnetic layers is a pinned layer with a magnetization direction fixed by exchange coupling with an adjacent anti-ferromagnetic (AFM) layer. The second ferromagnetic layer is a free layer in which the magnetic direction can be changed by applying external magnetic fields generated by a word line (WL) and bit line (BL). The electrical resistance for tunneling current across the tunnel barrier layer depends on the relative magnetic directions of the pinned and free layers. When the magnetic direction of the free layer is parallel to that of the pinned layer, the resistance across the tunnel barrier layer is low (“0” magnetic state), and when the direction of the free layer is anti-parallel to that of the pinned layer, the resistance across the tunnel barrier is high (“1” magnetic state). Thus, the high and low resistances across the tunnel barrier layer are directly related to the magnetic states of the MTJ cell and this relationship is referred to as a magnetoresistance effect that can be used to store binary information. The arrangement of the free layer above the tunnel barrier layer and pinned layer is called a bottom spin valve configuration. The positions of the free layer and pinned layer (and AFM layer) may be switched such that the free layer is between the tunnel barrier layer and bottom electrode (BE) in a top spin valve configuration.
Typically, there is a plurality of MRAM cells formed in an array on a substrate with a MTJ cell formed at each location where a bit line crosses over a word line. There are other devices including transistors and diodes below the MTJ cell and WL as well as peripheral circuits used to select certain MRAM cells within the MRAM array for read or write operations. Transistors and diodes are typically located about three to five layers below the WL level circuit.
The resistance of the MTJ cell can be altered to either high or low by one pair of the conducting lines below and above the MTJ cell. The conducting line below the MTJ cell is usually referred to as a word line and the conducting line over the MTJ cell is typically called a bit line. The word line level circuit includes two major elements which are a word line to conduct electric current and generate a WL magnetic field, and word line contact (WLC) to connect the MTJ cell to circuits below the WL metal level. Note that the WL and MTJ cell are separated by an insulating layer of dielectric (ILD) that typically is a composite with a lower etch stop layer and a relatively thick dielectric layer above the etch stop layer, but the BL and the MTJ cell are electrically connected through a top electrode. All of the conducting lines and vias are insulated by dielectric layers (ILDs).
The tunneling current provided by the transistors (not shown) formed on a silicon substrate to sense the resistance of a MTJ cell starts at the transistors and flows in the interconnects below the WL layer and into a WLC before passing through an overlying bottom electrode (BE), MTJ cell, and into a BL. A bottom electrode is one of the metal bridges connecting a MTJ cell with the rest of the semiconductor circuits and a second bridge is a top electrode that connects the MTJ cell to an overlying BL. A BE consists of two parts with different morphology. One portion including the region below the MTJ cell is flat and smooth to support good film uniformity in the MTJ cell while another portion is a metal contact inside a via hole called word line via (WLV) that is non-planar and is connected to a WLC to conduct a sensing current.
According to a common sense and basic physics principles, the greater the electric current density in a WL, the stronger the magnetic field generated by the WL, and the easier to change to magnetoresistance in an adjacent MTJ cell. Thus, a proper WL metallization is extremely critical since it must be capable of conducting high density current and used inexpensively within standard IC manufacturing technology. Copper is the best metal to satisfy the aforementioned requirements since it has the second highest electrical conductivity (59.6×106 S/m) of any element (just below silver) and is relatively cheap. For the sake of convenience and as a cost savings measure, all other conducting elements on the WL level including WLC are made of Cu, too. Since the WL level circuit is metalized with Cu, the ILD between the WL layer and BE not only insulates these two conducting layers, but also functions as a barrier layer to prevent WL copper from diffusing out of metal lines and contacts.
One must also consider that the closer the WL level is to a MTJ cell, the stronger will be the magnetic field generated by the WL on the free layer in the MTJ which makes changing the magnetoresistance state in the MTJ easier to accomplish. Although a WL should be as close as possible to a MTJ cell for ease of switching its magnetic state, a WL should be kept a minimum distance away from the MTJ (and BE) to allow an adequate thickness of ILD to prevent electrical shorting between the conductive elements. An increasing number of advanced MRAM designs require a thinner ILD between WL metal and a bottom electrode than is possible with a composite ILD used in the prior art. An improved ILD must satisfy three conditions which are (1) act as a good insulator to insulate WL metal from a bottom electrode; (2) serve as a good barrier to prevent copper diffusion; and (3) satisfy conditions (1) and (2) as a thin film to maximize the effect of a WL magnetic field on an overlying MTJ.
In an alternative technology called STT-MRAM, a spin-torque (spin transfer) effect is used to switch free layer magnetization instead of WL and BL currents in conventional MRAM. When a spin-polarized current transverses a magnetic multilayer in a current perpendicular to plane (CPP) configuration, the spin angular moment of electrons incident on a ferromagnetic layer interacts with magnetic moments of the ferromagnetic layer near the interface between the ferromagnetic and non-magnetic spacer. Through this interaction, the electrons transfer a portion of their angular momentum to the ferromagnetic layer. As a result, spin-polarized current can switch the magnetization direction of the ferromagnetic layer if the current density is sufficiently high, and if the dimensions of the multilayer are small.
Although conventional methods used to fabricate a WLV in an ILD opening on a Cu surface appear to be straightforward, there are several related issues that can easily lead to low manufacturing yields and device failure in both MRAM and STT-MRAM devices. For example, the Cu metal in the WLC is exposed to ILD etching plasma during an over-etch process and also to oxygen plasma during stripping of photoresist and BARC layers. Unfortunately, the residues created in these plasma processes are harmful to a Cu metal surface in a WLC thereby preventing a high quality WLV interconnection. In FIG. 1, residues and redepositions remaining after WLV etching and photoresist/BARC stripping that expose Cu metal to plasma are illustrated as particles 108a, 108b formed respectively on an ILD 103 and within the edge 107 of a WLV that uncovers a top surface 115s of a WLC. As mentioned in U.S. Pat. No. 7,157,415, if residues from dielectric etching and photoresist/BARC stripping are not cleaned away before the final step of forming openings that expose Cu metal such as when ILD etching to form a WLV is done without completely removing photoresist and BARC, then various residues may be formed on the metal surface and along the sidewall of the opening (via). Residues are usually complicated and contain Cu, CuO, Cu2O, and other materials. A post etch wet cleaning treatment is required to clean various types of etch residues consisting of CFX, CHFX, and the like, Cu, CuO, Cu2O, as well as back sputtered Cu on the dielectric surface and via sidewall. Since typical cleaning solutions containing dilute HF are ineffective in removing copper oxides or CFX compounds, the persistent copper oxides remain on the substrate and increase via metal resistance.
A prior art reference (U.S. Pat. No. 6,521,542) provides a detailed process for making Cu dual damascene structures where at least two layers of dielectrics are deposited on exposed Cu lines and vias of a prior interconnection level. The dielectric layer contacting exposed Cu in a lower level is used as an etch stop, and a thicker dielectric layer formed on the etch stop serves as the main insulating dielectric in which Cu lines and vias will be formed in the new metal level. All of the etching processes including the main etch through the thick ILD, photoresist and BARC stripping, and removal of filler used to protect the etch stop layer are completed before the thin etch stop layer is etched to expose the underlying Cu interconnect. A common practice as described in this reference and in U.S. Pat. Nos. 7,115,517, 7,157,415, and 6,809,028 is to perform the etch through the thick dielectric with a high DC bias and fast etch rate, strip the photoresist and BARC, and then switch to a lower DC bias and slow etch rate to remove the thin etch stop. Therefore, the photoresist and BARC layers are removed before exposing Cu metal in the lower interconnect to avoid formation of various complex residues as pictured in FIG. 1b. 
U.S. Pat. No. 6,174,737 teaches that the ILD should be etched to form windows for depositing a conductor (BE layer) which is used to connect the WLC to a MTJ but there are no suggestions regarding how to etch the patterned ILD or how to resolve issues associated with the etching processes.
U.S. Pat. No. 7,335,960 emphasizes the advantage of forming BL and WL close to the MTJ but the method of achieving this design and related fabrication issues are not disclosed. Therefore, in advanced interconnect structures designed for high performance where copper layers might be exposed to plasma etch chemistries during device fabrication, an integrated method for ILD etching, stripping a photoresist mask, and cleaning is needed so that troublesome residues can be avoided and a high quality WLV to WLC contact can be achieved.